In Verilog HDL, which option is the correct interpretation of the following statement? assign bus [7:4] = {bus [0], bus [1], bus[2], bus[3] } ;

A、bus[0], bus[1], bus[2] and bus[3] are assigned to bus[4], bus[5], bus[6] and bus[7] respectively;

B、bus[0], bus[1], bus[2] and bus[3] are assigned to bus[7], bus[6], bus[5] and bus[4] respectively;

C、The values of bus[0], bus[1], bus[2] and bus[3] remain unchanged;

D、All the values of bus[0], bus[1], bus[2] and bus[3] become binary 0